lunes, 21 de junio de 2010

A 2D scanning MEMS mirror from ASTRI


This micro-mechanical scanning mirror has drawn wide attention recently as its combination with diode light sources (e.g., laser diodes) provides a promising solution for mini image projectors, which can be integrated in portable electronics. The combination of a large scanning angle at a high resonant frequency but low actuation power is essential for this application.

Resonant 2D scanning mirrors, whose rotation is actuated by vertical electrostatic combs and can enable the out-of-plane rotation both in x- and y- direction by a gimbal structure , are very attractive in the application of mini image projectors due to their simple driving mechanism and fabrication process. An electrostatically (ES) actuated 2D scanning mirror is shown in Figure 1

Figure 1: An electrostatically actuated 2D scanning mirror. Insert: A SEM (scanning electron microscope) picture of the 2D scanning mirror


Coventor's Architect software is employed to build a 3D model of the device. A simplified schematic of the model is shown in Figure 2. Mirror plate, supported by a pair of 'Beam' components, was modeled using 'Rigid Plate' component from the Architect parts library. The electrical driving force was applied to the mirror by the component 'Comb Stator'. A 2D model was realized by adding another set of 'Rigid Plate', 'Beam' and 'Comb Stator', which represent the gimbal structure.
Figure 2: Schematic of a 2D scanning mirror.


As it is known that the motion of the mirror is highly nonlinear, Architect is used to simulate the transient frequency response instead of solving complicated ordinary differentiate equation. The mirror response due to a down sweeping frequency of an excitation source is shown in Figure 3

Figure 3: Transient response of one-axis of the 2D scanning mirror. A frequency down sweep is applied

Indeed, the response of the mirror to the down and up sweeping frequency is different and there exists hysteresis. This could be predicted by Architect and the results, as shown in Figure 4, are compared with the experimental one measured from a fabricated 2D mirror. It is shown that the Architect model is a fantastic tool for device simulation and further design optimization. An animation of the transient response of a 2D scanning mirror is shown in Figure 5.

Figure 4: Comparisons of Architect's results with the experimental one.

Figure 5. An animation of the transient response.

Nombre: Lenny D. Ramirez C.
Asignatura: CRF
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Process Simulation vs. Process Emulation: is SEMulator3D really TCAD?

I was interested to note that Silvaco has recently listed SEMulator3D as a competitor for their VICTORY Process Cell software on their website. It's great to be mentioned as a contender in the TCAD process simulation space. But I'd like to take the opportunity to examine the following question – are SEMulator3D and VICTORY Process Cell really direct competitors?

On the surface, both SEMulator3D and VICTORY Process Cell can do some similar things. Both tools are fast, layout driven process modeling engines that are designed to build 3D models of MEMS and semiconductor devices. Both tools can model individual process steps or entire process sequences, and can model a variety of process and device types. And both tools can create meshes suitable for further physics simulation.
Figure 1: A 3D MEMS Actuator, fabricated using the SCREAM process [1]. Left - Silvaco Process Cell

But despite the superficial similarities, there is an important distinction to be made between process simulation and process emulation. Process Cell and its direct competitors (Synopsys Sentaurus Process and similar) are process simulation tools and are based on TCAD simulation technology. The word "simulation" is key here because these tools simulate process steps using physical process models, driven by physical input parameters (implant energies, etch times and temperatures, etc). The models generated by these tools are well suited for detailed simulation of transistor electrical performance. But due to the complexity of the models, the chip area that can be modeled is relatively small – usually a single transistor, or at most a single layout cell. And because of their TCAD heritage, process simulation tools are often driven by a scripting language (powerful but can be difficult to learn).

SEMulator3D, on the other hand, is a process emulation tool. SEMulator3D creates models of process steps using geometric parameters – parameters that describe the shape, thickness, or depth of individual processing steps. While not as fundamental as physical parameters, geometric parameters are easier to determine (for example, can be extracted from a SEM of a device). SEMulator3D is driven by an easy to use graphical interface, freeing users to think about processing issues rather than script syntax. And SEMulator3D is uniquely capable of modeling large areas of silicon, measured in microns rather than nanometers.

Figure 2: A MEMS threshold accelerometer, fabricated using a dissolved wafer process and Silicon/glass wafer boding SEM image reproduced with permission of the author (Arjun Selvakumar). On the right is a SEMulator3D model.

So what does this all mean? From my perspective, it means that both process simulation and emulation are useful, but for different tasks.

3D process simulation (TCAD) is ideally suited for detailed device simulation – and for detailed electrical performance simulation - of individual devices or perhaps single cells.

In contrast, 3D process emulation (SEMulator3D) is ideally suited for fast 3D model generation, visualization, process/layout verification, and especially communication. Since SEMulator3D is fast and easy to use, it's a great way to communicate about processing topics within the fab. Process engineers and integration teams can save wafers by validating their process and layout before fabbing. And since SEMulator3D supports document creation in a number of standard formats, it's a great tool for process documentation.

So when you look at these two tools in a bit more detail, they are really quite different. Both are useful and capable, but in different ways. Perhaps both tools will find a niche in the process development cycle and combine to make process development more efficient and profitable

Nombre: Lenny D. Ramirez C.
Asignatura: CRF
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Process modeling of MEMS + IC DLP Mirror Device


Coventor software tools provide effective solutions for designing "MEMS+IC" devices. SEMulator3D offers the ability to build 3-dimensional models of complex MEMS structures and CMOS circuits as well as visualize the electrical connectivity between circuits and the MEMS devices with which they interact. One of the best known examples of a monolithically integrated CMOS circuit and MEMS device is Texas Instruments Digital MicroMirror Device, wherein MEMS digital light switches are rotated by electrostatic attraction depending on the state of an underlying SRAM cell.

Isometric and Cross Section View of single pixel model created with SEMulator3D

The following images show SEM photomicrographs (courtesy of Texas Instruments) and the equivalent SEMulator3D model view.

Ion Mill & SEMulator3D model Cross Section

DMD with mirror removed (Left: SEM image, right: SEMulator3D model)

Each DMD is addressed by an SRAM memory cell. SEMulator3D can effectively model both the underlying CMOS circuit as well as the MEMS device integrated above it. The following image shows an example 6T SRAM CMOS model - before the micromirror is built.

(top left) Exploded view of DLP mirror and memory cell. (bottom left) 6T SRAM. (top right) 3D model of circuitry. (bottom right) top view of MEMS DLP 3D model.

Once the complete model is built, the SEMulator3D Viewer allows you to visualize the model in terms of its electrical connectivity. As such, you can see to which part of the circuit each address electrode connects - in 3D - with the ability to rotate, zoom, explode and physically manipulate the model to verify that your design is correct.

Nombre: Lenny D. Ramirez C.
Asignatura: CRF
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There is CAD and than there is MEMS CAD


Choosing the right structural analysis method for MEMS simulations

MEMS designers are asked to generate MEMS models for circuit simulators such as SPICE in order for IC-designers to design control and read-out circuits for MEMS devices and optimize the two together. The three options available for creating such MEMS models are:

1.Hand-crafted analytical models

2.Create macro models extracted from Finite Element simulations

3.Discrete element representation using Network Models

These MEMS models need to describe the MEMS behavior accurately in the mechanical domain and electrical domain.
Each method has its advantages and disadvantage:

Analytical hand-crafted models

■Easy model creation - NO (depending on complexity and knowledge)

■Fast simulations - YES (for simple models)

■Accuracy - NO (Idealized models, lots of assumptions)

■Parametric - YES

■Complexity - NO

■Easy integration into IC tools - NO (manually)

FEM based macro-modeling

■Easy model creation - NO (Long simulation time and model validation)

■Fast simulation - YES (only for linear, simple models)

■Accuracy - NO (missing non-linearity, multi-physics)

■Parametric - NO

■Complexity - NO (partitioning in abstract macro-models)

■Easy integration into IC tools - NO (manually)

Network Models

■Easy model creation - YES (the geometry defines the models)

■Fast simulation - YES (fastest models compatible with ICs)

■Accuracy - YES (includes non-linearity, coupled multi-physics)

■Parametric - YES (100% parameterization of models)

■Complexity - YES (unlimited 3-D stacking and layouts)

■Easy integration into IC tools - YES (fully automated)

The diagram below shows the different methods of mechanical structural analysis along with other methods of analysis as described in [1].

Methods of structural analysis
The analytical method (1) is usually limited to simple models for which a closed form solution can be found; for example one dimensional linear deflection of an idealized beam under a point load. Usually these models are not sufficient to be used for MEMS design. These models also lead to misconceptions; it is for example often assumed that the pull-in voltage of a MEMS device occurs at 1/3 of the gap width which is only true for idealized "mass-spring-parallel plate capacitor" system.

The numerical solution of differential equations is usually limited to simple structures.

Also Finite Element based simulators (2) have their limitations and are not compatible with circuit simulators. There are clear disadvantages of using Reduced Order Modeling or Macro-Model extraction techniques since the resulting models are non-parameterized, often limited to structural analysis only and can not model non-linearity very well.

Since the goal is to connect the MEMS models with IC simulators the most natural choice is the "network method (3)" since it can be directly integrated with circuit simulations. In order to use the network method the MEMS device or structure is decomposed into an assembly of discrete structural elements with assumed form of displacement and the complete solution is then obtained by combining these individual approximate displacements in a manner which satisfies the force-equilibrium at the junctions of these elements. Methods based on this approach appear to be suitable for the analysis of complex structures. The theory of matrix structural analysis is ideally suited to numerically solve this type of analysis.

Nombre: Lenny D. Ramirez C.
Asignatura: CRF
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MEMSCAP PolyMUMPs MEMS Variable Capacitor Design


Variable Capacitor
The PolyMUMPS varactor is a gap-tuning structure, see image below and schematic below. The design consists of a three parallel-plates with the central one suspended by T-shaped arms between two fixed electrodes. One electrode lies on the silicon substrate coated with nitride (poly 0), the second rigidly suspended above the mobile plate (poly 2). Thus the device consist of two variable capacitors in series. One is used for RF applications (e.g. a VCO) and the other is considered as a parasitic. (The one with the smallest capacitance which means the bottom capacitor in this case).

3D Solid model in CoventorWare DESIGNER

Hierarchical schematic in CoventorWare ARCHITECT3D of the Variable Capacitor.

For process related questions a much more detailed 3D model and cross sections are often needed.

Process accurate 3D model in SEMulator3D

Voltage controlled oscillator

A voltage controlled oscillator (VCO) can be constructed from the variable capacitor. The schematic is shown below and is based on a cross-coupled PMOS architecture with 2 LC tank resonators.

VCO with 2 variable MEMS capacitors

Nombre: Lenny D. Ramirez C.
Asignatura: CRF
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Very Fast MEMS Gyro Simulation

If you are working on the next generation gyroscope design take a look at this article presented by Coventor at the APCOM 2007 conference in Kyoto, Japan.

This paper explains the modeling behind CoventorWare-ARCHITECT which will allow you to go further than just plain and simple resonance frequency analysis in Finite Element Software. The biggest problem for Gyro designers is getting past the initial stage. Once the design is analyzed for matching frequencies the design questions get tougher; what is the driving voltage, can I lower my noise floor, etc. In order to answer these questions and more you can't use your Finite Element models anymore because they just take to long to run, you need to add the sensing electrostatic fields and even worse, you need to run transient (i.e. time dependent) simulations with your Sigma-Delta circuit!

The paper describes a modeling technique that uses Finite Element definitions for the 3D mechanics as shown in the figure below:

Figure 1: Schematic model of a MEMS gyroscope with illustrations of the physical geometry represented by some of the schematic symbols.

However, the method they use to simulate the 3D electro-mechanical model is based on Matrix Algebra which does not solve all the internal stresses and strains of the gyro but does compute the force and displacement equilibriums correctly. That's what makes this method so fast and lets you simulate in the time domain including electronic components.

The schematic from the paper models the full 3D electrostatic-mechanical model as shown in this figure:

Figure 2: 3D view of a MEMS schematic model of a double mass gyroscope generated with Scene3D
Nombre: Lenny D. Ramirez C.
Asignatura: CRF
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Modeling and Simulation of an RF MEMS Switch Bouncing


This example shows an ohmic RF switch with gold dimples, which make contact with transmission lines upon electrostatic actuation. The voltage waveform used for electrostatic actuation should be designed very carefully so as to prevent the switch from bouncing after impact. The switch bouncing will lead to electrical discontinuities and increased wear. Figure 1 shows the 3D model of the RF switch.The RF switch consists of a center plate suspended by four folded beams. The plate has four tabs, namely NE, NW, SE and SW. The dimples at the bottom of the tabs make contact with waveguide once the switch closes.

Figure 1 : 3D model of the RF switch


Architect is used to build a fully parametric 3D model of the RF switch using L-beams, rigid plates and electrodes from the Parameterized Electromechanical Parts Library.Figure 2 shows the schematic of the RF switch.

Figure 2: RF switch schematic in Architect

The center plate of the switch behaves as a rigid body and is modeled using 'Rigid Plate' component from Architect Parts library. Rectangular and quadrilateral plates have been used to define the geometry of the plate and the tabs. The four dimples are also modeled using rigid plates and are labeled as 'Dimple TL', 'Dimple TR', 'Dimple BL' and 'Dimple BR'. The electrode beneath the center plate is modeled using 'Electrode' component from the library. The folded beams are modeled using a combination of 'L-Beam' and 'Beam' components. A 'Rigid Plate Damper' is used to model the effect of squeezed film damping.


Figure 3 shows the result of a transient simulation in Architect. The figure plots the soft landing waveform (a pulse with a magnitude of 190 volts and 500 nanoseconds rise and fall time) and the Z displacement of the plate center versus time. You can see the plate makes contact at around 30 microseconds. The plate remains in the displaced position till 150 microseconds. As the voltage is reduced to 0 Volts, the plate is released and bounces back. You can see that the plate bounce dies out over the next 450 microseconds due to damping. A fully coupled electro-mechanical transient simulation with contact and damping effects takes just 1 minuteto run on a 2GHz laptop.

Figure 3: Transient simulation in Architect

Figure 4 shows an animation of the transient analysis. This animation has been created using Scene3D. For clarity, the electrodes are transparent and the displacement in Z is scaled by a factor of 2.

Figure 4: Animation of Transient simulation

Nombre: Lenny D. Ramirez C.
Asignatura: CRF
Dirección http
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Electrostatic Pull-In Modeling of a MEMS Ring Gyroscope Structure

Modeling Pull-In behavior of MEMS devices is one of the essential technologies needed to design Electro-Mechanical devices. Over the years many papers have been published on analytical models for Pull-In behavior, most of which deal with simple beam like structures.
An alternative to closed form analytical solutions people use special MEMS multi-domain Finite Element Methods or Boundary Element Methods. These simulation tools give very accurate results but are limited by simulation times.

A different simulation technique, behavioral modeling, can achieve the same accuracy as Finite Element methods but with simulation speeds 100x or 1000x faster.

A detailed application note on modeling and simulating a ring gyro can be found on the Coventor Application Gallery pages.

Have a look at this example which has curved beams with curved electrodes underneath. The animation shows a time-sequence of a ring structure under increased voltage load, contact to the electrode and release of the structure after the voltage is removed.

Visualization of behavioral model Pull In simulation

Nombre: Lenny D. Ramirez C.
Asignatura: CRF
Dirección http
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MEMS relays as logic gates. Really?

Posted by Mattan Kamon
Even if I didn't say it, that is what I was thinking when I was approached after a talk I gave at the International Solid State Circuits Conference (ISSCC) in the "Fusion of MEMS and Circuits" session last month. The person who approached me was Matthew Spencer, a contributor on a program to use MEMS relays to realize ultra-low-power VLSI circuits [1,2,3]. He was excited about the possibilities of what our new product, MEMS+, could do for him. What exactly are they trying to do with these MEMS switches and logic? What could I have said in my talk to inspire this interest? Was his excitement warranted? I'll try to answer that in the rest of this post.

What are they trying to do for VLSI?
Matt sent me their papers after I returned from the conference [1,2,3]. And the answer to my title question is "Really!". The work is impressive and is the result of a combined effort at UC Berkeley, MIT, and UCLA. Just as MEMS RF-switches have advantages in high isolation and low insertion loss over solid-state devices, MEMS as logic gates have zero leakage in the off-state and high on-state current compared to other CMOS alternatives for ultra-low-power [1]. The device is a switch plate with a folded flexure design as shown here (posted with permission from the authors):

The switch closes at around a 10 volt gate-to-body voltage difference and closes in about 100 ns. These gates can then be assembled into circuits to create logic functions such as part of an adder that generates the carry bit (posted with permission from the authors):

A and B are, say, the 4's digit from two binary numbers. Cin is any "carry" from adding the 2's digit. Cout is the carry digit to be sent to the 8's digit. The above example demonstrates a VLSI logic function but in order to create a VLSI logic application, the logic must communicate, and for this the authors demonstrate using the switches for I/O and analog-to-digital/digital-to-analog conversion.

What did I say in my talk that could help this effort?

They hope to design logic circuits with 10's to 100's of these gates in the near term. That design process requires simulation, and to simulate these large circuits they need a good model of their switch within their circuit environment of choice, in this case Cadence Virtuoso. Matt had been tasked with creating this model, and over the past year he's gone through quite an "ordeal", as Matt put it, to create a model in Verilog-A. It doesn't model all the physics he'd like and its robustness is suspect but it does allow them to simulate a handful of switches in a minute or so of simulation.

My talk suggested a possible route for Matt to end his ordeal. The first few slides of my talk at the ISSCC conference described the larger vision for MEMS+ as a shared platform for MEMS and IC that integrates into IC and system level design flows. However, as the rest of my talk described, what we've executed most rigorously in this first release of MEMS+ is the straightforward manner of creating a circuit-level model directly from a physical description of the device. The approach relies on hints during design entry of the MEMS device that indicate the physical behavior of that section of the device. One is effectively creating a 3D schematic. The procedure is detailed in the MEMS+ video tutorial on our website. Since MEMS+ goes directly from description to model without lengthy finite-element analysis, the models can be made parametric with respect to design variables so a designer can easily explore changing dimensions or environmental conditions, such as temperature, without recreating the model.

Was the interest warranted?

I was intrigued with this new application for MEMS and MEMS+ and wanted to see just how quickly I could put together something useful with this new tool we in Coventor R&D have worked so hard to create. Given just the papers, which lacked many of the dimensions and material properties, I put together the following quick-and-dirty 3-D schematic of their design in somewhere between 1 and 2 hours of my time:

that time was spent reviewing the papers and mapping that to the appropriate components and design dimensions. Note I carefully made it parametric with respect to the design dimensions such as gate size and drain width so that one could explore changing those dimensions from within the circuit simulation environment. Also note that the electrical interface was carefully defined for the eventual simulation model.

I then imported the model into a the Cadence Virtuoso Library Manager (a 5 minute process), placed an instance of the new symbol, built a little test harness of voltage sources and got my first simulation in about 15 minutes of my time:

Above you see the rather boring square symbol for the switch with the 6 electrical pins exposed from the MEMS+ 3D-view (the 7th pin at the top is a mechanical pin for the z position of the gate). Inset below the symbol are some of the properties of the instance. Notice those were automatically created to give access to the MEMS+ 3D-view's design dimensions. Matt had indicated he had his own contact resistance model, so I put a 1K resistor between the contacts and turned off our own contact resistance model. I also put a 1K resistor at the source so there would be a non-floating voltage to measure (not really necessary in retrospect). I swept the gate voltage and observed contact at around 7 volts (not shown). This doesn't match the paper's value of 10 volts, but is good enough (don't forget I didn't know many of the dimensions (something I will leave Matt to do)).
The figure on the right shows a transient simulation for one on/off cycle of 10 volts applied to the gate. This shows the position of the gate over time. You can see around 10us the gate closed, but bounced a number of times before settling. It first made contact at 400 ns, which is in the right ballpark from the paper (100 ns). The simulation took a handful of CPU seconds (maybe 30, I don't quite remember).

Are we done? No. The above model would be good for MEMS design studies. For instance, I could run parameter sweeps on the design dimensions to understand how to optimize the dimensions to get greater contact force or faster switching times. However, the goal here is to simulate many of these switches together, so we'd like to optimize this model for speed at the expense of some of the details such as the bouncing. Matt even indicated that bouncing isn't an issue for them at the moment.

To that end, I spent about 2 or 3 hours tinkering with some of the knobs we provide to trade accuracy for speed. For instance, the switch's gate in the above simulation could move in all 3 translation directions (x,y,z) as well as rotate about the 3 axes. For this study, we don't need to tax the simulator by tracking the motion of all 6 degrees of freedom, so I fixed the plate to only move in z. By doing so, we also know that the gap between gate and body is uniform and so the electrostatic computation need only account for the holes and edges, not a non-uniform gap. I also added a custom contact damper to absorb the bouncing since much of the time spent was in resolving the many bounces:
Which gave the following:

The entire simulation shown took only 0.230 CPU seconds. And this is on a Linux Dell Precision 380 (circa 2005). Some more recent desktop hardware is about 4x faster. The far-right plot shows that once contact was made, the switch between drain and source was closed and the voltage at the source jumped as desired. (The astute observer will notice that the source voltage output is not 10 volts. I was getting significant parasitic actuation between the drain and the floating contact dimple so I lowered the drain voltage for this demo. Of course that force is actually there but I must have guessed contact dimples that were too large. Again, something for Matt to get right).

With a functional logic gate, we are ready to connect these together to build a logic circuit.

The voltage sources and source resistor were removed from the schematic above to create a cell-view for a single logic gate with gate, source, drain, and body terminals. The cell instances were then placed to create the carry generation circuit shown before:
Which, in 3 CPU seconds, on circa 2005 desktop hardware, generates a good carry bit for all the input combinations:


The above showed that with about 7 hours of work, a model capturing the fundamental electromechanical behavior of this switch could be created directly from design parameters and then tweaked for simulation speed within the Cadence Virtuoso environment. Multiple instances of this model could be assembled to simulate a small logic circuit in a few seconds with the Cadence Spectre simulator.

Many of the dimensions were guessed, however the part that made this an "ordeal" for Matt within Verilog-A is clearly not an ordeal for MEMS+.

Much could still be done from here. Obviously the design dimensions must be entered correctly. From that, a useable layout pCell could be created automatically. In addition, other features could be modeled to make this more accurate, such as nonlinear damping, stiction force, and parasitic actuation due to the drain-to-gate voltage.

Nombre: Lenny D. Ramirez C.
Asignatura: CRF

Solutions for testing MEMS devices at the wafer level

Solutions for testing MEMS devices at the wafer level


The MEMS industry is growing rapidly, but early testing is still much neglected. At a glance, manufacturing MEMS devices and classic ICs seem quite similar, but the behavior of MEMS devices is much more complex than classic ICs and differs owing to the MEMS devices having additional mechanical, mostly moveable, parts and packages that are generally a large portion of their cost.

There are many reasons why testing prior to packaging is beneficial: The packaging process is very costly. Failed devices that are tested after final packaging waste not only money but R&D, process utilization, and foundry time. Performing functional tests, reliability investigations, and failure analysis at an early stage of the production is vital for the commercialization of the microsystems as it will reduce production costs and time to market.

Test goals by phase

Each of the three phases of the MEMS product development lifecycle has unique test goals and requirements with very different results.

In the product R&D phase, proving the device works and that it can be manufactured. In this phase, wafer-level test enables early device characterization, which reduces development time and, of course, development costs up to 15%. In addition, reliability issues are of a major importance for the successful commercialization of the MEMS device. Therefore wafer-level test in the R&D phase is essential.

In the pilot production phase, the goals are to prove manufacturability in high-yield volumes and to develop a production-equipment solution as well as establish testing needs for volume. Here, both development time and costs can be reduced through on-wafer test.

In the volume production phase, the goals are to maximize throughput and reduce costs. Since the typical yield of MEMS production is much lower than in the IC production, and since cost breakdowns show that 60% to 80% of manufacturing costs are incurred during and after packaging, early-stage test provides a significant cost reduction for the volume production of MEMS (see Fig. 1). The real cost savings depend on the actual production environment and the type of the MEMS component.

Fig. 1. Early testing of MEMS devices can reduce cost and improve yield.

However beneficial early testing may be, standard, off-the-shelf test equipment has been difficult for most manufacturers to find. In addition to electrical stimulation and electrical measurement, devices may require testing using sound, light, vibration, fluidics, pressure, temperature, chemical, or force stimulation.

As a result of this input stimulation, the test engineer may need to measure any of these categories in addition to detecting and measuring mechanical, optical, or electrical signals generated as a result of this stimulation. The devices may require testing in a controlled atmosphere to protect the device from environmental damage or to correctly simulate the environment in which the device will operate once packaged.

MEMS test equipment types

Since 2000, wafer-level test technology and equipment has been available from SUSS MicroTec that enables on-wafer test of pressure sensors, RF MEMS, resonators, micromirrors, gas sensors, microbolometers, and much more. The equipment was developed in conjunction with new MEMS test technologies and was mostly customer driven.

Current wafer-level MEMS test systems are based on two platforms: open and closed. In the semiconductor industry, wafer-level tests are performed by the use of wafer probers. The devices on the wafer have to be reliably contacted by a probe card or single probes and electrically connected to the tester.

Such systems are limited in their ability to perform MEMS tests, but by adding appropriate modules for non-electrical stimulation and/or detection of nonelectrical outputs, the wafer prober can be extended to an open, universal test platform that can be easily reconfigured according to the test requirements (see Fig. 2). This open platform is well suited for testing differential and absolute pressure sensors, microphones and micromirrors.
Fig. 2. Open test systems like the PA200 with PPM and MSA-500 can be reconfigured to suit test requirements.

Wafer-level test of MEMS devices that are designed for operation in vacuum or a specific gas environment need such an environment for the test phase. Additionally, studies of the growing reliability problems can not be evaluated on open systems; they require precisely controlled test environments.

To perform these tests at wafer-level, it is necessary to place the wafer prober inside a chamber (see Fig. 3). The chamber can be evacuated or filled with different gases and the pressure can be varied between high vacuum and a small positive pressure during ongoing tests. Simultaneously, the wafer temperature in the vacuum prober can be controlled between –60° and 200°C or in a cryogenic version even down to 77K (liquid nitrogen) or 4.2K (liquid helium).

Similar to the open platform, suitable modules for non-electrical stimulation and/or detection of non-electrical output values can be added to the closed platform. This closed platform is particularly useful for testing RF MEMS, MEMS resonators, microbolometers, and inertial sensors like accelerometers and gyroscopes.

Fig. 3. A vacuum prober provides a closed, tightly controlled environment for reliability evaluations.

Ongoing efforts

Future tasks for the MEMS industry include test standardization for both final packaged test as well as wafer-level test, the definition of design rules for simplifying the test of MEMS device, and the expansion of equipment and technology platforms to cover future MEMS devices.

Formed to meet the challenges of wafer-level MEMS testing, MEMUNITY is an open community of MEMS testing experts from industry, research institutions, and academia. As a result of leveraging the expertise and know-how contained within MEMUNITY, several developments in wafer-level test technologies were achieved within the past two years, including the world's only pressure chamber probe system.
Recently, MEMUNITY finished coordinating the PAR-TEST project, which aimed to define the behavior of materials used in the production of MEMS devices and make them accessible to engineers. More specifically, advanced measurement techniques were developed that will enable engineers to determine the quality parameters of materials used in the production of MEMS devices—parameters that are critical for process control.

One of the results of the MEMUNITY-coordinated PAR-TEST project was the development of a one-of-a-kind integrated wafer-level test system for MEMS devices that use a moveable membrane such as in pressure sensors. The platform for the system was a semiautomatic probe system (the SUSS PA200) that provides precise, automated positioning and wafer mapping, an electrostatic probe card to stimulate the membrane, and a laser-Doppler vibrometer (the Polytec MSA-500) to measure out-of-plane movement. The membrane's characteristics are extracted by measuring the eigenfrequencies and the resulting information is used to optimize the device design and the manufacturing process, as well as for known-good/bad die test.

Nombre: Lenny D. Ramirez C.
Asignatura: CRF
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