MEMS technology is based on a number of tools and methodologies, which are used to form small structures with dimensions in the micrometer scale (one millionth of a meter). Significant parts of the technology has been adopted from integrated circuit (IC) technology. For instance, almost all devices are build on wafers of silicon, like ICs. The structures are realized in thin films of materials, like ICs. They are patterned using photolithographic methods, like ICs. There are however several processes that are not derived from IC technology, and as the technology continues to grow the gap with IC technology also grows.
There are three basic building blocks in MEMS technology, which are the ability to deposit thin films of material on a substrate, to apply a patterned mask on top of the films by photolithograpic imaging, and to etch the films selectively to the mask. A MEMS process is usually a structured sequence of these operations to form actual devices. Please follow the links to read more about deposition, lithography and etching.
MEMS Thin Film Deposition Processes
One of the basic building blocks in MEMS processing is the ability to deposit thin films of material. In this text we assume a thin film to have a thickness anywhere between a few nanometer to about 100 micrometer. The film can subsequently be locally etched using processes described in the Lithography and Etching sections of this guide.
MEMS deposition technology can be classified in two groups:
1. Depositions that happen because of a chemical reaction:
o Chemical Vapor Deposition (CVD)
o Thermal oxidation
These processes exploit the creation of solid materials directly from chemical reactions in gas and/or liquid compositions or with the substrate material. The solid material is usually not the only product formed by the reaction. Byproducts can include gases, liquids and even other solids.
2. Depositions that happen because of a physical reaction:
o Physical Vapor Deposition (PVD)
Common for all these processes are that the material deposited is physically moved on to the substrate. In other words, there is no chemical reaction which forms the material on the substrate. This is not completely correct for casting processes, though it is more convenient to think of them that way.
This is by no means an exhaustive list since technologies evolve continuously.
Chemical Vapor Deposition (CVD)
In this process, the substrate is placed inside a reactor to which a number of gases are supplied. The fundamental principle of the process is that a chemical reaction takes place between the source gases. The product of that reaction is a solid material with condenses on all surfaces inside the reactor.
The two most important CVD technologies in MEMS are the Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (PECVD). The LPCVD process produces layers with excellent uniformity of thickness and material characteristics. The main problems with the process are the high deposition temperature (higher than 600°C) and the relatively slow deposition rate. The PECVD process can operate at lower temperatures (down to 300° C) thanks to the extra energy supplied to the gas molecules by the plasma in the reactor. However, the quality of the films tend to be inferior to processes running at higher temperatures. Secondly, most PECVD deposition systems can only deposit the material on one side of the wafers on 1 to 4 wafers at a time. LPCVD systems deposit films on both sides of at least 25 wafers at a time. A schematic diagram of a typical LPCVD reactor is shown in the figure below.
Figure 1: Typical hot-wall LPCVD reactor.
When do I want to use CVD?
CVD processes are ideal to use when you want a thin film with good step coverage. A variety of materials can be deposited with this technology, however, some of them are less popular with fabs because of hazardous byproducts formed during processing. The quality of the material varies from process to process, however a good rule of thumb is that higher process temperature yields a material with higher quality and less defects.
This process is also known as "electroplating" and is typically restricted to electrically conductive materials. There are basically two technologies for plating: Electroplating and Electroless plating. In the electroplating process the substrate is placed in a liquid solution (electrolyte). When an electrical potential is applied between a conducting area on the substrate and a counter electrode (usually platinum) in the liquid, a chemical redox process takes place resulting in the formation of a layer of material on the substrate and usually some gas generation at the counter electrode.
In the electroless plating process a more complex chemical solution is used, in which deposition happens spontaneously on any surface which forms a sufficiently high electrochemical potential with the solution. This process is desirable since it does not require any external electrical potential and contact to the substrate during processing. Unfortunately, it is also more difficult to control with regards to film thickness and uniformity. A schematic diagram of a typical setup for electroplating is shown in the figure below.
When do I want to use electrodeposition?
The electrodeposition process is well suited to make films of metals such as copper, gold and nickel. The films can be made in any thickness from ~1µm to >100µm. The deposition is best controlled when used with an external electrical potential, however, it requires electrical contact to the substrate when immersed in the liquid bath. In any process, the surface of the substrate must have an electrically conducting coating before the deposition can be done.
Figure 2: Typical setup for electrodeposition.
This technology is quite similar to what happens in CVD processes, however, if the substrate is an ordered semiconductor crystal (i.e. silicon, gallium arsenide), it is possible with this process to continue building on the substrate with the same crystallographic orientation with the substrate acting as a seed for the deposition. If an amorphous/polycrystalline substrate surface is used, the film will also be amorphous or polycrystalline.
There are several technologies for creating the conditions inside a reactor needed to support epitaxial growth, of which the most important is Vapor Phase Epitaxy (VPE). In this process, a number of gases are introduced in an induction heated reactor where only the substrate is heated. The temperature of the substrate typically must be at least 50% of the melting point of the material to be deposited.
An advantage of epitaxy is the high growth rate of material, which allows the formation of films with considerable thickness (>100µm). Epitaxy is a widely used technology for producing silicon on insulator (SOI) substrates. The technology is primarily used for deposition of silicon. A schematic diagram of a typical vapor phase epitaxial reactor is shown in the figure below.
Figure 3: Typical cold-wall vapor phase epitaxial reactor.
When do I want to use epitaxy?
This has been and continues to be an emerging process technology in MEMS. The process can be used to form films of silicon with thicknesses of ~1µm to >100µm. Some processes require high temperature exposure of the substrate, whereas others do not require significant heating of the substrate. Some processes can even be used to perform selective deposition, depending on the surface of the substrate.
This is one of the most basic deposition technologies. It is simply oxidation of the substrate surface in an oxygen rich atmosphere. The temperature is raised to 800° C-1100° C to speed up the process. This is also the only deposition technology which actually consumes some of the substrate as it proceeds. The growth of the film is spurned by diffusion of oxygen into the substrate, which means the film growth is actually downwards into the substrate. As the thickness of the oxidized layer increases, the diffusion of oxygen to the substrate becomes more difficult leading to a parabolic relationship between film thickness and oxidation time for films thicker than ~100nm. This process is naturally limited to materials that can be oxidized, and it can only form films that are oxides of that material. This is the classical process used to form silicon dioxide on a silicon substrate. A schematic diagram of a typical wafer oxidation furnace is shown in the figure below.
When do I want to use thermal oxidation?
Whenever you can! This is a simple process, which unfortunately produces films with somewhat limited use in MEMS components. It is typically used to form films that are used for electrical insulation or that are used for other process purposes later in a process sequence.
Figure 4: Typical wafer oxidation furnace.
Physical Vapor Deposition (PVD)
PVD covers a number of deposition technologies in which material is released from a source and transferred to the substrate. The two most important technologies are evaporation and sputtering.
When do I want to use PVD?
PVD comprises the standard technologies for deposition of metals. It is far more common than CVD for metals since it can be performed at lower process risk and cheaper in regards to materials cost. The quality of the films are inferior to CVD, which for metals means higher resistivity and for insulators more defects and traps. The step coverage is also not as good as CVD.
The choice of deposition method (i.e. evaporation vs. sputtering) may in many cases be arbitrary, and may depend more on what technology is available for the specific material at the time.
In evaporation the substrate is placed inside a vacuum chamber, in which a block (source) of the material to be deposited is also located. The source material is then heated to the point where it starts to boil and evaporate. The vacuum is required to allow the molecules to evaporate freely in the chamber, and they subsequently condense on all surfaces. This principle is the same for all evaporation technologies, only the method used to the heat (evaporate) the source material differs. There are two popular evaporation technologies, which are e-beam evaporation and resistive evaporation each referring to the heating method. In e-beam evaporation, an electron beam is aimed at the source material causing local heating and evaporation. In resistive evaporation, a tungsten boat, containing the source material, is heated electrically with a high current to make the material evaporate. Many materials are restrictive in terms of what evaporation method can be used (i.e. aluminum is quite difficult to evaporate using resistive heating), which typically relates to the phase transition properties of that material. A schematic diagram of a typical system for e-beam evaporation is shown in the figure below.
Figure 5: Typical system for e-beam evaporation of materials.
Sputtering is a technology in which the material is released from the source at much lower temperature than evaporation. The substrate is placed in a vacuum chamber with the source material, named a target, and an inert gas (such as argon) is introduced at low pressure. A gas plasma is struck using an RF power source, causing the gas to become ionized. The ions are accelerated towards the surface of the target, causing atoms of the source material to break off from the target in vapor form and condense on all surfaces including the substrate. As for evaporation, the basic principle of sputtering is the same for all sputtering technologies. The differences typically relate to the manor in which the ion bombardment of the target is realized. A schematic diagram of a typical RF sputtering system is shown in the figure below.
Figure 6: Typical RF sputtering system.
In this process the material to be deposited is dissolved in liquid form in a solvent. The material can be applied to the substrate by spraying or spinning. Once the solvent is evaporated, a thin film of the material remains on the substrate. This is particularly useful for polymer materials, which may be easily dissolved in organic solvents, and it is the common method used to apply photoresist to substrates (in photolithography). The thicknesses that can be cast on a substrate range all the way from a single monolayer of molecules (adhesion promotion) to tens of micrometers. In recent years, the casting technology has also been applied to form films of glass materials on substrates. The spin casting process is illustrated in the figure below.
When do I want to use casting?
Casting is a simple technology which can be used for a variety of materials (mostly polymers). The control on film thickness depends on exact conditions, but can be sustained within +/-10% in a wide range. If you are planning to use photolithography you will be using casting, which is an integral part of that technology. There are also other interesting materials such as polyimide and spin-on glass which can be applied by casting.
Figure 7: The spin casting process as used for photoresist in photolithography.
Lithography in the MEMS context is typically the transfer of a pattern to a photosensitive material by selective exposure to a radiation source such as light. A photosensitive material is a material that experiences a change in its physical properties when exposed to a radiation source. If we selectively expose a photosensitive material to radiation (e.g. by masking some of the radiation) the pattern of the radiation on the material is transferred to the material exposed, as the properties of the exposed and unexposed regions differs (as shown in figure 1).
Figure 1: Transfer of a pattern to a photosensitive material.
This discussion will focus on optical lithography, which is simply lithography using a radiation source with wavelength(s) in the visible spectrum.
In lithography for micromachining, the photosensitive material used is typically a photoresist (also called resist, other photosensitive polymers are also used). When resist is exposed to a radiation source of a specific a wavelength, the chemical resistance of the resist to developer solution changes. If the resist is placed in a developer solution after selective exposure to a light source, it will etch away one of the two regions (exposed or unexposed). If the exposed material is etched away by the developer and the unexposed region is resilient, the material is considered to be a positive resist (shown in figure 2a). If the exposed material is resilient to the developer and the unexposed region is etched away, it is considered to be a negative resist (shown in figure 2b).
Figure 2: a) Pattern definition in positive resist, b) Pattern definition in negative resist.
Lithography is the principal mechanism for pattern definition in micromachining. Photosensitive compounds are primarily organic, and do not encompass the spectrum of materials properties of interest to micro-machinists. However, as the technique is capable of producing fine features in an economic fashion, a photosensitive layer is often used as a temporary mask when etching an underlying layer, so that the pattern may be transferred to the underlying layer (shown in figure 3a). Photoresist may also be used as a template for patterning material deposited after lithography (shown in figure 3b). The resist is subsequently etched away, and the material deposited on the resist is "lifted off".
The deposition template (lift-off) approach for transferring a pattern from resist to another layer is less common than using the resist pattern as an etch mask. The reason for this is that resist is incompatible with most MEMS deposition processes, usually because it cannot withstand high temperatures and may act as a source of contamination.
Figure 3: a) Pattern transfer from patterned photoresist to underlying layer by etching, b) Pattern transfer from patterned photoresist to overlying layer by lift-off.
Once the pattern has been transferred to another layer, the resist is usually stripped. This is often necessary as the resist may be incompatible with further micromachining steps. It also makes the topography more dramatic, which may hamper further lithography steps.
In order to make useful devices the patterns for different lithography steps that belong to a single structure must be aligned to one another. The first pattern transferred to a wafer usually includes a set of alignment marks, which are high precision features that are used as the reference when positioning subsequent patterns, to the first pattern (as shown in figure 4). Often alignment marks are included in other patterns, as the original alignment marks may be obliterated as processing progresses. It is important for each alignment mark on the wafer to be labeled so it may be identified, and for each pattern to specify the alignment mark (and the location thereof) to which it should be aligned. By providing the location of the alignment mark it is easy for the operator to locate the correct feature in a short time. Each pattern layer should have an alignment feature so that it may be registered to the rest of the layers.
Figure 4: Use of alignment marks to register subsequent layers
Depending on the lithography equipment used, the feature on the mask used for registration of the mask may be transferred to the wafer (as shown in figure 5). In this case, it may be important to locate the alignment marks such that they don't effect subsequent wafer processing or device performance. For example, the alignment mark shown in figure 6 will cease to exist after a through the wafer DRIE etch. Pattern transfer of the mask alignment features to the wafer may obliterate the alignment features on the wafer. In this case the alignment marks should be designed to minimize this effect, or alternately there should be multiple copies of the alignment marks on the wafer, so there will be alignment marks remaining for other masks to be registered to.
Figure 5: Transfer of mask registration feature to substrate during lithography (contact aligner)
Figure 6: Poor alignment mark design for a DRIE through the wafer etch (cross hair is released and lost).
Alignment marks may not necessarily be arbitrarily located on the wafer, as the equipment used to perform alignment may have limited travel and therefore only be able to align to features located within a certain region on the wafer (as shown in figure 7). The region location geometry and size may also vary with the type of alignment, so the lithographic equipment and type of alignment to be used should be considered before locating alignment marks. Typically two alignment marks are used to align the mask and wafer, one alignment mark is sufficient to align the mask and wafer in x and y, but it requires two marks (preferably spaced far apart) to correct for fine offset in rotation.
Figure 7: Restriction of location of alignment marks based on equipment used.
As there is no pattern on the wafer for the first pattern to align to, the first pattern is typically aligned to the primary wafer flat (as shown in figure 8). Depending on the lithography equipment used, this may be done automatically, or by manual alignment to an explicit wafer registration feature on the mask.
Figure 8: Mask alignment to the wafer flat.
The exposure parameters required in order to achieve accurate pattern transfer from the mask to the photosensitive layer depend primarily on the wavelength of the radiation source and the dose required to achieve the desired properties change of the photoresist. Different photoresists exhibit different sensitivities to different wavelengths. The dose required per unit volume of photoresist for good pattern transfer is somewhat constant; however, the physics of the exposure process may affect the dose actually received. For example a highly reflective layer under the photoresist may result in the material experiencing a higher dose than if the underlying layer is absorptive, as the photoresist is exposed both by the incident radiation as well as the reflected radiation. The dose will also vary with resist thickness.
There are also higher order effects, such as interference patterns in thick resist films on reflective substrates, which may affect the pattern transfer quality and sidewall properties.
At the edges of pattern light is scattered and diffracted, so if an image is overexposed, the dose received by photoresist at the edge that shouldn't be exposed may become significant. If we are using positive photoresist, this will result in the photoresist image being eroded along the edges, resulting in a decrease in feature size and a loss of sharpness or corners (as shown in figure 9). If we are using a negative resist, the photoresist image is dilated, causing the features to be larger than desired, again accompanied by a loss of sharpness of corners. If an image is severely underexposed, the pattern may not be transferred at all, and in less sever cases the results will be similar to those for overexposure with the results reversed for the different polarities of resist.
Figure 9: Over and under-exposure of positive resist.
If the surface being exposed is not flat, the high-resolution image of the mask on the wafer may be distorted by the loss of focus of the image across the varying topography. This is one of the limiting factors of MEMS lithography when high aspect ratio features are present. High aspect ratio features also experience problems with obtaining even resist thickness coating, which further degrades pattern transfer and complicates the associated processing.
The Lithography Module
Typically lithography is performed as part of a well-characterized module, which includes the wafer surface preparation, photoresist deposition, alignment of the mask and wafer, exposure, develop and appropriate resist conditioning. The lithography process steps need to be characterized as a sequence in order to ensure that the remaining resist at the end of the modules is an optimal image of the mask, and has the desired sidewall profile.
The standard steps found in a lithography module are (in sequence): dehydration bake, HMDS prime, resist spin/spray, soft bake, alignment, exposure, post exposure bake, develop hard bake and descum. Not all lithography modules will contain all the process steps. A brief explanation of the process steps is included for completeness.
• Dehydration bake - dehydrate the wafer to aid resist adhesion.
• HMDS prime - coating of wafer surface with adhesion promoter. Not necessary for all surfaces.
• Resist spin/spray - coating of the wafer with resist either by spinning or spraying. Typically desire a uniform coat.
• Soft bake - drive off some of the solvent in the resist, may result in a significant loss of mass of resist (and thickness). Makes resist more viscous.
• Alignment - align pattern on mask to features on wafers.
• Exposure - projection of mask image on resist to cause selective chemical property change.
• Post exposure bake - baking of resist to drive off further solvent content. Makes resist more resistant to etchants (other than developer).
• Develop - selective removal of resist after exposure (exposed resist if resist is positive, unexposed resist if resist is positive). Usually a wet process (although dry processes exist).
• Hard bake - drive off most of the remaining solvent from the resist.
• Descum - removal of thin layer of resist scum that may occlude open regions in pattern, helps to open up corners.
We make a few assumptions about photolithography. Firstly, we assume that a well characterized module exists that: prepares the wafer surface, deposits the requisite resist thickness, aligns the mask perfectly, exposes the wafer with the optimal dosage, develops the resist under the optimal conditions, and bakes the resist for the appropriate times at the appropriate locations in the sequence. Unfortunately, even if the module is executed perfectly, the properties of lithography are very feature and topography dependent. It is therefore necessary for the designer to be aware of certain limitations of lithography, as well as the information they should provide to the technician performing the lithography.
The designer influences the lithographic process through their selections of materials, topography and geometry. The material(s) upon which the resist is to be deposited is important, as it affects the resist adhesion. The reflectivity and roughness of the layer beneath the photoresist determines the amount of reflected and dispersed light present during exposure. It is difficult to obtain a nice uniform resist coat across a surface with high topography, which complicates exposure and development as the resist has different thickness in different locations. If the surface of the wafer has many different height features, the limited depth of focus of most lithographic exposure tools will become an issue (as shown in figure 10).
Figure 10: Lithography tool depth of focus and surface topology.
The designer should keep all these limitations in mind, and design accordingly. For example, it is judicious, when possible, to perform very high aspect patterning step (lithography and subsequent etch/deposition) last, as the topography generated often hampers any further lithography steps. It is also necessary for the designer to make it clear which focal plane is most important to them (keeping in mind that features further away in Z from the focal plane will experience the worst focus). The resolution test structures should be located at this level (as they will be used by the fab to check the quality of a photo step).
In order to form a functional MEMS structure on a substrate, it is necessary to etch the thin films previously deposited and/or the substrate itself. In general, there are two classes of etching processes:
1. Wet etching where the material is dissolved when immersed in a chemical solution
2. Dry etching where the material is sputtered or dissolved using reactive ions or a vapor phase etchant
In the following, we will briefly discuss the most popular technologies for wet and dry etching.
This is the simplest etching technology. All it requires is a container with a liquid solution that will dissolve the material in question. Unfortunately, there are complications since usually a mask is desired to selectively etch the material. One must find a mask that will not dissolve or at least etches much slower than the material to be patterned. Secondly, some single crystal materials, such as silicon, exhibit anisotropic etching in certain chemicals. Anisotropic etching in contrast to isotropic etching means different etch rates in different directions in the material. The classic example of this is the <111> crystal plane sidewalls that appear when etching a hole in a <100> silicon wafer in a chemical such as potassium hydroxide (KOH). The result is a pyramid shaped hole instead of a hole with rounded sidewalls with a isotropic etchant. The principle of anisotropic and isotropic wet etching is illustrated in the figure below.
When do I want to use wet etching?
This is a simple technology, which will give good results if you can find the combination of etchant and mask material to suit your application. Wet etching works very well for etching thin films on substrates, and can also be used to etch the substrate itself. The problem with substrate etching is that isotropic processes will cause undercutting of the mask layer by the same distance as the etch depth. Anisotropic processes allow the etching to stop on certain crystal planes in the substrate, but still results in a loss of space, since these planes cannot be vertical to the surface when etching holes or cavities. If this is a limitation for you, you should consider dry etching of the substrate instead. However, keep in mind that the cost per wafer will be 1-2 orders of magnitude higher to perform the dry etching
If you are making very small features in thin films (comparable to the film thickness), you may also encounter problems with isotropic wet etching, since the undercutting will be at least equal to the film thickness. With dry etching it is possible etch almost straight down without undercutting, which provides much higher resolution.
Figure 1: Difference between anisotropic and isotropic wet etching.
The dry etching technology can split in three separate classes called reactive ion etching (RIE), sputter etching, and vapor phase etching.
In RIE, the substrate is placed inside a reactor in which several gases are introduced. A plasma is struck in the gas mixture using an RF power source, breaking the gas molecules into ions. The ions are accelerated towards, and reacts at, the surface of the material being etched, forming another gaseous material. This is known as the chemical part of reactive ion etching. There is also a physical part which is similar in nature to the sputtering deposition process. If the ions have high enough energy, they can knock atoms out of the material to be etched without a chemical reaction. It is a very complex task to develop dry etch processes that balance chemical and physical etching, since there are many parameters to adjust. By changing the balance it is possible to influence the anisotropy of the etching, since the chemical part is isotropic and the physical part highly anisotropic the combination can form sidewalls that have shapes from rounded to vertical. A schematic of a typical reactive ion etching system is shown in the figure below.
A special subclass of RIE which continues to grow rapidly in popularity is deep RIE (DRIE). In this process, etch depths of hundreds of microns can be achieved with almost vertical sidewalls. The primary technology is based on the so-called "Bosch process", named after the German company Robert Bosch which filed the original patent, where two different gas compositions are alternated in the reactor. The first gas composition creates a polymer on the surface of the substrate, and the second gas composition etches the substrate. The polymer is immediately sputtered away by the physical part of the etching, but only on the horizontal surfaces and not the sidewalls. Since the polymer only dissolves very slowly in the chemical part of the etching, it builds up on the sidewalls and protects them from etching. As a result, etching aspect ratios of 50 to 1 can be achieved. The process can easily be used to etch completely through a silicon substrate, and etch rates are 3-4 times higher than wet etching.
Sputter etching is essentially RIE without reactive ions. The systems used are very similar in principle to sputtering deposition systems. The big difference is that substrate is now subjected to the ion bombardment instead of the material target used in sputter deposition.
Vapor phase etching is another dry etching method, which can be done with simpler equipment than what RIE requires. In this process the wafer to be etched is placed inside a chamber, in which one or more gases are introduced. The material to be etched is dissolved at the surface in a chemical reaction with the gas molecules. The two most common vapor phase etching technologies are silicon dioxide etching using hydrogen fluoride (HF) and silicon etching using xenon diflouride (XeF2), both of which are isotropic in nature. Usually, care must be taken in the design of a vapor phase process to not have bi-products form in the chemical reaction that condense on the surface and interfere with the etching process.
When do I want to use dry etching?
The first thing you should note about this technology is that it is expensive to run compared to wet etching. If you are concerned with feature resolution in thin film structures or you need vertical sidewalls for deep etchings in the substrate, you have to consider dry etching. If you are concerned about the price of your process and device, you may want to minimize the use of dry etching. The IC industry has long since adopted dry etching to achieve small features, but in many cases feature size is not as critical in MEMS. Dry etching is an enabling technology, which comes at a sometimes high cost.
Figure 2: Typical parallel-plate reactive ion etching system.
MEMS and Nanotechnology is currently used in low- or medium-volume applications.
Some of the obstacles preventing its wider adoption are:
Most companies who wish to explore the potential of MEMS and Nanotechnology have very limited options for prototyping or manufacturing devices, and have no capability or expertise in microfabrication technology. Few companies will build their own fabrication facilities because of the high cost. A mechanism giving smaller organizations responsive and affordable access to MEMS and Nano fabrication is essential.
The packaging of MEMS devices and systems needs to improve considerably from its current primitive state. MEMS packaging is more challenging than IC packaging due to the diversity of MEMS devices and the requirement that many of these devices be in contact with their environment. Currently almost all MEMS and Nano development efforts must develop a new and specialized package for each new device. Most companies find that packaging is the single most expensive and time consuming task in their overall product development program. As for the components themselves, numerical modeling and simulation tools for MEMS packaging are virtually non-existent. Approaches which allow designers to select from a catalog of existing standardized packages for a new MEMS device without compromising performance would be beneficial.
Fabrication Knowledge Required
Currently the designer of a MEMS device requires a high level of fabrication knowledge in order to create a successful design. Often the development of even the most mundane MEMS device requires a dedicated research effort to find a suitable process sequence for fabricating it. MEMS device design needs to be separated from the complexities of the process sequence.
How the MEMS and Nanotechnology Exchange Can Help
The MEMS and Nanotechnology Exchange provides services that can help with some of these problems.
• We make a diverse catalog of processing capabilities available to our users, so our users can experiment with different fabrication technologies. We also have a number of novel processes that are difficult to obtain from other fabrication services.
• Our users don't have to build their own fabrication facilities, and
• Our web-based interface lets users assemble process sequences and submit them for review by the MEMS and Nanotechnology Exchange's engineers and fabrication sites.
GREINER A. GONZALEZ G.